//================================================================================================
// File Name   : sram_wrap.sv
// Designer    : Peng Wei
// Mail        : peng.wei@wingsemitech.com
// Create Time : Mon Sep 11 20:22:19 2023
// Description :
// 
//  * mem_ctrl connect following pins
//    * mem_ctrl[2:0] = EMA[2:0],  input, Extra margin adjustment. 000 is the fastest.
//    * mem_ctrl[4:3] = EMAW[1:0], input, Extra margin adjustment for write operations.
//    * mem_ctrl[5]   = EMAS,      input, Extra margin adjustment for sense amplifier pulse.
//    * mem_ctrl[6]   = STOV,      input, Self-timed pulse override, for testing purposes only.
// 
//  * mem_lp connect following pins
//    * mem_lp[0] = PGEN, Power-down enable to enter Power Down or retention modes, active-HIGH.
//    * mem_lp[1] = RET1N, Retention mode 1 enable, active-LOW
//    * mem_lp[2] = RET2N, Retention mode 2 enable, active-LOW
//  
//  TMEM
//  * mem_lp connect following pins
//    * mem_lp[0] = Sleep-mode    ,active-HIGH.
//    * mem_lp[1] = Shut-down mode,active-HIGH
//
//================================================================================================

`include "wing_cbb_define_dff.sv"
`include "wing_cbb_define_misc.sv"

module sram_wrap #(
    parameter   DEPTH   = 4096,
    parameter   DATA_W  = 32,
    // DO NOT MODIFY FOLLOWING DERIVATIVE PARAMETERS !
    parameter   ADDR_W  = $clog2(DEPTH)
)(
  input  logic                    clk,
  input  logic                    rst_n,
  input  logic [15:0]             mem_ctrl,
  input  logic [15:0]             mem_dft,
  input  logic [15:0]             mem_lp,
  input  logic                    scan_en,

  input  logic                    cs,
  input  logic                    wr,     // 1'b1: write, 1'b0: read
  input  logic [ADDR_W-1:0]       addr,
  input  logic [DATA_W-1:0]       wdata,
  input  logic [DATA_W-1:0]       wen,
  output logic [DATA_W-1:0]       rdata
);

//=================================================================================
// Clock Gate
//=================================================================================

logic gated_clk;

wing_cbb_icg_wrap u_gated_clk (
    .clk        (clk             ),
    .clk_en     (cs              ),
    .scan_en    (scan_en         ),
    .gated_clk  (gated_clk       )
);

wing_cbb_mem_sim #(
  .DEPTH        ( DEPTH   ),
  .DATA_W       ( DATA_W  ),
  .WSTB_RATIO_N ( 1       )
) u_mem_model (
  .clk   ( clk   ),
  .cs    ( cs    ),
  .wr    ( wr    ),
  .addr  ( addr  ),
  .wdata ( wdata ),
  .we    ( wen   ),
  .rdata ( rdata )
);

endmodule
